The escalating requirements for high densification and performance associated with ultra-large scale integration semiconductor devices requires design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. Such requirements have been found difficult to satisfy in terms of providing low RC (Resistance Capacitance) interconnect patterns. Moreover, as design features are reduced to about 0.25 microns and under, processing defects which were either not apparent or of little impact on device performance become apparent and/or adversely impact device performance, thereby generating an unacceptable rejection rate.
Conventional semiconductor manufacturing methodology comprises forming low resistance cobalt disilicide (CoSi.sub.2) layers at electrical interconnection points, such as on polycrystalline silicon gate electrodes and/or source/drain regions formed in a silicon semiconductor substrate. Typically, a layer of cobalt is deposited, as by physical vapor deposition (PVD) on the gate electrode and/or source/drain regions. A capping layer containing titanium is then deposited on the cobalt layers to prevent oxygen in the atmosphere from diffusing into the cobalt disilicide layer during the silicidation reaction, thereby preventing an undesirable increase in resistivity. Annealing is then conducted at an elevated temperature during which silicidation occurs, i.e., cobalt reacts with the underlying silicon to form a CoSi.sub.2 low resistivity layer. The titanium-containing capping layer is then removed.
It was found, however, that titanium from the capping layer undesirably reacts with cobalt in the underlying layer and diffuses into the silicide layer forming a mixed layer of titanium disilicide (TiSi.sub.2) and CoSi.sub.2 having an undesirable high resistivity. In addition, it was found extremely difficult to selectively remove the titanium-containing capping layer without adversely impacting the underlying silicide layer.
Accordingly, there exists a need for semiconductor methodology to form low resistivity CoSi.sub.2 layers, particularly in manufacturing ultra-large scale integration and high density semiconductor devices with submicron design features, e.g., 0.25 microns and under.